Binary-weighted capacitor arrays or ladders are commonly employed in analog-to-digital converters, digital-to-analog converters, switched-capacitor filters, and the like. The ratio accuracy, matching, and tracking requirements for capacitor ladders are similar to those associated with resistor ladders of comparable bit resolution. Capacitor ladders comprise a plurality of capacitors, arranged in a parallel combination of binary-weighted component values. Capacitor structures commonly employed in capacitor ladders include conventional metal oxide semiconductors (MOS) structures or double-polysilicon (i.e., polysilicon-oxide-polysilicon) structures. With MOS technology, it is relatively straightforward to realize capacitors of precise capacitance values. Junction capacitors are not suitable for charge-scaling applications due to relatively poor matching characteristics and voltage dependence.
The requirements for capacitor ladders are virtually identical to those for switched-capacitor filters; namely, accurate control of capacitor ratios and minimization of the effects of bottom-plate parasitics. The ratio accuracy is optimized by forming arrays of identical unit-geometry capacitors, which are then interconnected to obtain the desired ratios. The effect of bottom-plate parasitics are minimized by coupling the bottom plates to a voltage source. For example, the potential of the bottom plates can be switched between ground and a reference voltage, whereas the top plates thereof can be connected together to a common output bus.
Capacitors forming an array are generally designed to optimize ratio matching. Deviance from ratio matching, i.e. ratio error, stems from three sources: (1) edge definition of the masking process; (2) top-plate parasitics due to metal interconnections and metal overlap over applied dielectric oxide; and (3) oxide thickness gradients across a chip. The limitation of edge-definition associated with the photomasking process contributes an error of approximately 0.1-0.2 micron uncertainty in the capacitor length and width dimensions. Normally, the relative uncertainty (.DELTA.X) placed in any edge dimension is relatively well-fixed by process tolerances. To minimize the effect of this uncertainty, the capacitor length (L) and width (W) ratios are normally chosen to be equal, and the capacitors are laid out as square sections, as shown in FIG. 1.
If direct area scaling is used to set the capacitor ratios, as shown in FIG. 1, the capacitor ratios become increasingly sensitive to the edge-definition error .DELTA.X as the capacitor area is reduced. This can be avoided by using the capacitor array approach shown in FIG. 2, where the capacitor ratios are scaled by interconnecting a number of capacitors of identical unit capacitance value. In this approach, edge-definition errors have a negligible effect on the ratio accuracy, since both the area and the periphery ratios are scaled simultaneously. The effect of top-plate parasitics due to interconnection lines can also be accounted for by proper scaling of the interconnection line lengths and widths between capacitors.
Top-plate edge parasitics are generated where there is a slight metal overlap of the top plate over the field dielectric, or where there is an undercutting of the mask which defines the capacitor. Another source of capacitor ratio accuracy error is due to the presence of long-range thickness gradients in the thin dielectric oxide. These gradients arise from non-uniform oxide growth conditions. If variation in oxide thickness is approximated as a first-order gradient, then the resulting ratio error is proportional to the fractional variation in oxide thickness. The oxide thickness gradients can vary as much as .+-.10 to .+-.100 parts per million (ppm) per millimeter of dimensional length along the chip surface.
The effects of these long-range gradients can be mitigated by using a common-centroid geometry in the layout and interconnection of the capacitor array. This is illustrated in FIG. 3, in which the elements of the capacitors are positioned such that they are symmetrically spaced about a common center point. For example unit capacitor elements 92A, 92B, 92C, 92D, contributing to the capacitance of capacitor C4, are positioned about central capacitor C1; as are unit capacitor elements 94A, 94B, which contribute to the capacitance of capacitor C2. In this manner, the capacitor ratio accuracy (i.e., the ratio between C1, C2, and C4) can still be maintained in spite of first-order gradients in the capacitor oxide thickness.
FIG. 4 is a schematic diagram illustrating a common-centroid layout of a capacitor array. As shown, among a bank of thirty capacitors 20, nine capacitors (within dashed line 10) are connected to nine corresponding switches 30 through metal lines 40, respectively. The remaining capacitors 11 and metal lines 41 are dummy capacitors and dummy metal lines, respectively. The dummy capacitors 11 are not used, but the dummy metal lines 41 are provided for minimizing the top-plate parasitic error.
Even though it nearly eliminates ratio error arising from the top-plate parasitic components due to metal overlap, the common-centroid layout does not reduce the top-plate parasitic components due to metal interconnections to a sufficient degree. Also, the common-centroid layout becomes cumbersome and wasteful of chip surface area if a higher order of symmetry is required. Therefore, this configuration is normally limited to the first several bits (low-order bits) of the capacitor ladder. As MOS technology advances, and capacitor sizes become smaller, the top-plate parasitics become more significant because, with such a high integration density, the parasitic capacitance may become larger in magnitude than the capacitance of a unit capacitor.